HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 787

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
21.4.8
The SIOF has one type of interrupt.
(1)
Interrupts can be issued by several sources. Each source is shown as an SIOF status in SISTR.
Table 21.12 lists the SIOF interrupt sources.
Table 21.12 SIOF Interrupt Sources
Whether an interrupt is issued or not as the result of an interrupt source is determined by the
SIIER settings. If an interrupt source is set to 1 and the corresponding bit in SIIER is set to 1, an
SIOF interrupt is issued.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
No. Classification
1
2
3
4
5
6
7
8
9
10
11
12
Interrupt Sources
Transmission
Reception
Control
Error
Interrupts
Bit Name
TDREQ
TFEMP
RDREQ
RFFUL
TCRDY
RCRDY
TFUDF
TFOVF
RFOVF
RFUDF
FSERR
SAERR
Function Name
Transmit FIFO transfer
request
Transmit FIFO empty
Receive FIFO transfer
request
Receive FIFO full
Transmit control data
ready
Receive control data
ready
Transmit FIFO
underflow
Transmit FIFO overflow Write to the transmit FIFO is
Receive FIFO overflow Serial data is received while the
Receive FIFO
underflow
FS error
Assign error
Description
The transmit FIFO stores data of
specified size or more.
The receive FIFO stores data of
specified size or more.
The transmit control register is ready
to be written.
The receive control data register
stores valid data.
Serial data transmit timing has arrived
while the transmit FIFO is empty.
performed while the transmit FIFO is
full.
receive FIFO is full.
The receive FIFO is read while the
receive FIFO is empty.
the specified bit number has been
passed (in slave mode).
serial data and control data.
The transmit FIFO is empty.
The receive FIFO is full.
A synchronous signal is input before
The same slot is specified in both
Section 21 Serial I/O with FIFO (SIOF)
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