HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 339

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
The bus state controller (BSC) outputs control signals for various types of memory that is
connected to the external address space and external devices. The BSC functions enable this LSI
to connect directly with SRAM, SDRAM, and other memory storage devices, and external
devices.
9.1
The BSC has the following features:
(1) External address space
• A maximum 32 or 64 Mbytes for each of the eight areas, CS0, CS2 to CS4, CS5A, CS5B,
• A maximum 64 Mbytes for each of the six areas, CS0, CS2 to CS4, CS5, and CS6, totally a
• Can specify the normal space interface, byte-selection SRAM, burst ROM (clock synchronous
• Can select the data bus width (8, 16, or 32 bits) for each address space.
• Controls the insertion of the wait state for each address space.
• Controls the insertion of the wait state for each read access and write access.
• Can set the independent idling cycle in the continuous access for five cases: read-write (in
(2) Normal space interface
• Supports the interface that can directly connect to the SRAM.
(3) Burst ROM (clock asynchronous) interface
• High-speed access to the ROM that has the page mode function.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
CS6A and CS6B, totally 384 Mbytes (divided into eight areas).
total of 384 Mbytes (divided into six areas).
or asynchronous), SDRAM, PCMCIA for each address space.
same space/different space), read-read (in same space/different space), or the first cycle is a
write access.
Features
Section 9 Bus State Controller (BSC)
Section 9 Bus State Controller (BSC)
Page 279 of 1414