HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 1058

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 30 SIM Card Module (SIM)
Page 998 of 1414
Bit
3
Bit Name
PER
Initial
Value
0
R/W
R/W
Description
Parity Error
Indicates that a parity error has occurred during reception,
resulting in abnormal termination.
0: Indicates that reception is in progress, or that reception
[Clearing conditions]
•
•
1: Indicates that a parity error occurred during reception*
[Setting condition]
When the sum of 1 bit in the received data and parity bit
does not match the even or odd parity specified by the O/E
bit in the serial mode register (SCSMR).
Notes:
was completed normally*
On reset
When 0 is written to the PER bit
1. When the RE bit in SCSCR is cleared to 0, the
2. In T = 0 mode, the data received when a parity
PER flag is unaffected, and the previous state
is retained.
error occurs is not transferred to SCRDR, and
the RDRF flag is not set.
On the other hand, in T = 1 mode, the data
received when a parity error occurs is
transferred to SCRDR, and the RDRF flag is
set.
When a parity error occurs, the PER flag should
be cleared to 0 before the sampling timing for
the next parity bit.
1
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
2