HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 803

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
(2)
ASTR2 is the register that is composed of interrupt status flag (2 bits) relating DAA control and
mask flag (2 bits) of interrupt signals for DAA control. Status flags shows statuses of ringing
detect interrupt, end of dial pulse output interrupt. Interrupt flags are cleared by 0 write after read
action of this register. Each Interrupt signal can be masked by each interrupt masks.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
0
Bit
15 to 10 ⎯
9
8
7 to 2
AFEIF Status Register 2 (ASTR2)
RHF
DPEM
RDETM
⎯
Bit Name
Bit Name
Initial Value
0
Initial Value
All 0
1
1
All 0
R/W
R
R/W
R
R/W
R/W
R
Description
Receive FIFO Half Size Full
0: Normal state
[Clearing conditions]
•
•
•
1: Rx FIFO half size interrupt
[Setting condition]
•
Description
Reserved
These bits are always read as 0. The write
value should always be 0.
Dial Pulse End Interrupt Mask
0: Interrupt enable
1: Interrupt mask
Ringing Detect Mask
0: Ringing interrupt enable
1: Ringing interrupt mask
Reserved
These bits are always read as 0. The write
value should always be 0.
Reset
Number of data in FIFO becomes smaller
than the half of the size that is indicated by
FFSZ
RE bit (ACTR1) is set to 0
The half of specified size with FFSZ
(ACTR1) of receive data is accumulated into
FIFO
Section 22 Analog Front End Interface (AFEIF)
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