HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 290

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 Exception Handling
(5)
• Conditions
• Types
• Save address
• Exception code
• Remarks
(6)
• Conditions
• Types
• Save address
• Exception code
Page 230 of 1414
When a break condition set in the user break controller is satisfied
Break (L bus) before instruction execution: Instruction synchronous, re-execution type
Operand break (L bus): Instruction synchronous, processing-completion type
Data break (L bus): Instruction asynchronous, processing-completion type
I bus break: Instruction asynchronous, processing-completion type
Re-execution type: An address of the instruction where a break occurs (a delayed branch
instruction address if an instruction is assigned to a delay slot)
Processing-completion type: An address of the instruction following the instruction where a
break occurs (a delayed branch instruction destination address if an instruction is assigned to a
delay slot)
H'1E0
For details on user break controller, refer to section 33, User Break Controller (UBC).
⎯ Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
⎯ Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n +
Instruction asynchronous, processing-completion type
An address of the instruction following the instruction where a break occurs (a delayed branch
instruction destination address if an instruction is assigned to a delay slot)
H'5C0
User break point trap
DMA address error
3)
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010