HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 571

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
14.4.3
The TMU generates underflow interrupts for each channel. When the interrupt request flag and
interrupt enable bit are both set to 1, the interrupt is requested. Codes are set in the interrupt event
register (INTEVT, INTEVT2) for these interrupts and interrupt processing must be executed
according to the codes.
The relative priorities between channels can be changed using the interrupt controller. For details,
refer to section 7, Exception Handling, and section 8, Interrupt Controller (INTC). Table 14.1 lists
TMU interrupt sources.
Table 14.1 TMU Interrupt Sources
Software standby mode can be cancelled by TSU_SUNI which is OR of an underflow interrupt for
each TMU channel. (It is available when the RTC output clock is selected as a counter input
clock.)
TMU_SUNI is processed as an interrupt which differs from an underflow interrupt for each
channel by the interrupt controller (INTC). Therefore, an underflow interrupt for each channel and
TMU_SUNI should be used differently.
When canceling software standby mode, set the bits 11 to 8 in interrupt priority register D (IPRD)
of INTC to any value and bits 15 to 4 in interrupt priority register A (IPRA) of INTC to H'000 so
that only the TMU_SUNI is accepted. In the TMU_SUNI interrupt routine, clear both the under
flow flag (UNF) in the timer control register (TCR) and the TMU_SUNI interrupt request bit
(TMU_SUNIR) in the interrupt request register 0 of INTC.
value so that an underflow interrupt can be accepted for each channel. For details, see section 8,
Interrupt Controller (INTC).
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Channel
0
1
2
In the normal operating state, set the bits 11 to 8 in IPRD to H'0 and bits 15 to 4 in IPRA to any
Interrupt Sources and Priorities
Interrupt Source
TUNI0
TUNI1
TUNI2
Description
Underflow interrupt 0
Underflow interrupt 1
Underflow interrupt 2
Priority
High
Low
Section 14 Timer Unit (TMU)
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