HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 56

SH3-DSP, WITH USB AND LCDC, PB-F

HD6417720BP133BV

Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417720BP133BV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Table 21.2
Table 21.3
Table 21.4
Table 21.5
Table 21.6
Table 21.7
Table 21.8
Table 21.9
Table 21.10
Table 21.11
Table 21.12
Section 22 Analog Front End Interface (AFEIF)
Table 22.1
Table 22.2
Table 22.3
Section 23 USB Pin Multiplex Controller
Table 23.1
Table 23.2
Table 23.3
Table 23.4
Section 24 USB Host Controller (USBH)
Table 24.1
Section 25 USB Function Controller (USBF)
Table 25.1
Table 25.2
Table 25.3
Table 25.4
Table 25.5
Section 26 LCD Controller (LCDC)
Table 26.1
Table 26.2
Table 26.3
Table 26.4
Page lvi of lx
Operation in Each Transfer Mode......................................................................... 685
SIOF Serial Clock Frequency ............................................................................... 710
Serial Transfer Modes........................................................................................... 713
Frame Length........................................................................................................ 714
Audio Mode Specification for Transmit Data....................................................... 716
Audio Mode Specification for Receive Data ........................................................ 716
Setting Number of Channels in Control Data ....................................................... 717
Conditions to Issue Transmit Request .................................................................. 719
Conditions to Issue Receive Request.................................................................... 720
Transmit and Receive Reset ................................................................................. 725
SIOF Interrupt Sources ......................................................................................... 727
Pin Configuration.................................................................................................. 736
FIFO Interrupt Size............................................................................................... 738
Telephone Number and Data ................................................................................ 745
Pin Configuration (Digital Transceiver Signal) .................................................... 756
Pin Configuration (Analog Transceiver Signal) ................................................... 756
Pin Configuration (Power Control Signal)............................................................ 757
Pin Configuration (Clock Signal) ......................................................................... 757
Pin Configuration.................................................................................................. 766
Pin Configuration and Functions .......................................................................... 805
Restrictions of Settable Values ............................................................................. 834
Example of Endpoint Configuration..................................................................... 834
Example of Setting of Endpoint Configuration Information ................................ 835
Command Decoding on Application Side ............................................................ 855
Pin Configuration.................................................................................................. 865
I/O Clock Frequency and Clock Division Ratio ................................................... 868
Limits on the Resolution of Rotated Displays, Burst Length,
and Connected Memory (32-bit SDRAM)............................................................ 899
Limits on the Resolution of Rotated Displays, Burst Length,
and Connected Memory (16-bit SDRAM)............................................................ 902
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010

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