HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 149

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
3.3
3.3.1
In DSP mode, a specific function is provided to execute repeat loops efficiently. By using this
function, loop programs can be executed without overhead caused by the compare and branch
instructions.
(1)
Examples of repeat loop programs are shown below.
• Example 1: Repeat loop consisting of 4 or more instructions
In the above program example, instructions from the RptStart address (instr1 instruction) to the
RptEnd address (instrN instruction) are repeated four times. These repeated instructions in the
program are called repeat loop. The start and end instructions of the repeat loop are called the
repeat start instruction and repeat end instruction, respectively. The CPU sequentially executes
instructions and starts repeat loop control if the CPU detects the completion of a specific
instruction. This specific instruction is called the repeat detection instruction. In a repeat loop
consisting of four or more instructions, an instruction three instructions prior to the repeat end
instruction is regarded as the repeat detection instruction. In a repeat loop consisting of four or
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
RptStart: instr1
RptDtct:
RptEnd2:
RptEnd1:
RptEnd:
Examples of Repeat Loop Programs
CPU Extended Instructions
DSP Repeat Control
LDRS RptStart
LDRE RptDtct +4
SETRC #4
Instr0
... ...
... ...
instr(N-3)
instr(N-2)
instr(N-1)
instrN
;Three instruction prior to the repeat
; Sets repeat start instruction address
to the RS register
; Sets the number of repetitions (4) to
the RC[11:0] bits of the SR register
; At least one instruction is required
from SETRC instruction to [Repeat start
instruction]
; [Repeat start instruction]
;
;
end instruction is regarded as repeat
detection instruction
;
;
; [Repeat end instruction]
; Sets (repeat detection instruction
address + 4) to the RE register
Section 3 DSP Operating Unit
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