HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 300

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 Exception Handling
Table 7.5
Note: The following labels are used here.
(5)
If an MMU exception occurs in the repeat control period, a specific exception code is generated as
well as a CPU address error. For a TLB miss exception, TLB invalid exception, and initial page
write exception, an exception code (H'070) indicating the repeat loop period is specified in the
EXPEVT. For a TLB protection exception, an exception code (H'0D0) is specified in the
EXPEVT. In a TLB miss exception, vector offset is specified as H'00000100.
An instruction where an exception occurs and the SPC value to be saved are the same as those for
the CPU address error.
After this exception processing, the repeat control cannot be returned correctly. To execute a
repeat loop correctly, care must be taken not to generate an MMU related exception in the repeat
control period.
Note: In a repeat loop consisting of one to three instructions, some restrictions apply to repeat
Page 240 of 1414
Instruction Where an
Exception Occurs
RptDtct
RptDtct1
RptDtct2
RptDtct3
MMU Exception in Repeat Control Period
RptDtct:
RptDtct1: Instruction address immediately after the repeat detect instruction
RptDtct2: Second instruction address from the repeat detect instruction
RptDtct3: Third instruction address from the repeat detect instruction
detection instructions and all the remaining instructions. In a repeat loop consisting of four
or more instructions, restrictions apply to only the three instructions that include a repeat
end instruction. The restriction occurs when SR.RC[11:0] ≥ 1.
Instruction Where a Specific Exception Occurs When a Memory Access
Exception Occurs in Repeat Control (SR.RC[11:0]≥1)
Repeat detection instruction address
1
⎯
Instruction/data
access
⎯
⎯
Number of Instructions in a Repeat Loop
2
⎯
Instruction/data
access
Instruction/data
access
⎯
3
⎯
Instruction/data
access
Instruction/data
access
Instruction/data
access
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
4 or Greater
⎯
Instruction/data
access
Instruction/data
access
Instruction/data
access
Sep 21, 2010