HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 550

SH3-DSP, WITH USB AND LCDC, PB-F

HD6417720BP133BV

Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417720BP133BV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Section 13 Power-Down Modes
13.4
13.4.1
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of the CPU registers remain unchanged. The on-chip peripheral
modules continue to operate in sleep mode and the clock continues to be output to the CKIO pin.
In sleep mode the output of the STATUS0 pin and STATUS1 pin go high and low, respectively.
13.4.2
Sleep mode is canceled by an interrupt (NMI, IRQ, IRL, PINT, and on-chip peripheral module) or
reset. Interrupts are accepted in sleep mode even when the BL bit in SR is 1. If necessary, save
SPC and SSR to the stack before executing the SLEEP instruction.
(1)
When an NMI, IRQ, IRL, PINT, or on-chip peripheral module interrupt occurs, sleep mode is
canceled and interrupt exception handling is executed. A code indicating the interrupt source is set
in INTEVT and INTEVT2.
(2)
Sleep mode is canceled by a power-on reset or a manual reset.
Page 490 of 1414
Canceling with Interrupt
Canceling with Reset
Sleep Mode
Transition to Sleep Mode
Canceling Sleep Mode
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010

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