HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 258
HD6417720BP133BV
Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.R8A77210C133BAV.pdf
(1478 pages)
Specifications of HD6417720BP133BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Section 5 Cache
Figure 5.1 shows the cache structure.
(1)
The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data
is not valid. The U bit indicates whether the entry has been written to in write-back mode. When
the U bit is 1, the entry has been written to; when 0, it has not. The tag address holds the physical
address used in the external memory access. It is composed of 22 bits (address bits 31 to 10) used
for comparison during cache searches.
In this LSI, the top three of 32 physical address bits are used as shadow bits (see section 9, Bus
State Controller (BSC)), and therefore the top three bits of the tag address are cleared to 0.
The V and U bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset.
The tag address is not initialized by either a power-on or manual reset.
(2)
Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes). The
data array is not initialized by a power-on or manual reset.
Page 198 of 1414
Address Array
Data Array
Entry 255
Entry 0
Entry 1
.
.
.
.
.
.
24 (1 + 1 + 22) bits
V U Tag address
Address array (ways 0 to 3)
Figure 5.1 Cache Structure
255
0
1
.
.
.
.
.
.
LW0 to LW3: Longword data 0 to 3
LW0
128 (32 × 4) bits
LW1
LW2
Data array (ways 0 to 3)
LW3
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
255
0
1
.
.
.
.
.
.
LRU
6 bits
Sep 21, 2010
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