HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 1158

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 31 MultiMediaCard Interface (MMCIF)
31.5.2
For transfer with DMAC, set MMCIF (DMACR) after setting DMAC. The FIFO ready flag is
generated after DMACR is set and data more than threshold set in DMACR is written to the FIFO.
Start transmission to the MMC after setting the flag. Figures 31.28 to 31.31 show the operational
flowcharts for write sequence in MMC mode.
• FIFO is cleared.
• Write command is transmitted.
• DMACR is set and write data is set to the FIFO.
• Confirmed that the data more than DMACR setting condition is written to the FIFO by the
• The end of the transfer with the DMAC is confirmed, and 0 is set to the DMAEN bit in
• When the CRC error (CRCERI) or the command timeout error (CTERI) occurs during
• When the CRC error (CRCERI), write error (WRERI), or data timeout error (DTERI) occurs
When the DMA is in use, an interrupt between blocks in pre-defined multiblock transfer can be
processed by hard by setting the AUTO bit in DMACR to 1. Figure 31.32 shows the operational
flowchart for pre-defined multi write sequence in MMC mode.
• FIFO is cleared.
• The number of blocks is set to TBNCR.
• The START bit in CMDSTRT is set to 1 and command transmission is started.
• Command response is received from the MMC.
• If the MMC does not return the command response, it detected by the command timeout error
• DMACR is set and write data is set to the FIFO.
• The end of the transfer with the DMAC is confirmed, and 0 is set to the DMAEN bit in
• Command sequence end is detected by polling the BUSY flag in CSTR or the multiblock
• Errors during command sequence (data transmission) are detected by the CRC error flag
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FIFO ready flag (FRDYI), or that all data is written to the FIFO by the DMAC, and then the
DATAEN bit in OPCR is set to 1 to start write data transmission.
DMACR.
command response reception, write 1 to the CMDOFF bit.
during write data transmission, 1 is written to the CMDOFF bit and DMACR is set to H'00 to
clear the FIFO.
flag (CTERI).
DMACR.
transfer (pre-defined) end flag (BTI).
(CRCERI) or the data timeout error flag. When interrupts are detected, set the CMDOFF bit in
OPCR to 1 to issue the CMD12 command and suspend the command sequence.
Operation of Write Sequence
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010