HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 376

SH3-DSP, WITH USB AND LCDC, PB-F

HD6417720BP133BV

Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417720BP133BV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Section 9 Bus State Controller (BSC)
(3)
• CS2WCR
• CS3WCR
Page 316 of 1414
Bit
31 to 9
8
7
6 to 0
Bit
31 to 15
14
13
12
SDRAM
Bit Name
A2CL1
A2CL0
Bit Name
TRP1
TRP0
Initial
Value
All 0
1
0
All 0
Initial
Value
All 0
0
0
0
R/W Description
R
R/W
R/W
R
R/W Description
R
R/W
R/W
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Cycles from Auto-Precharge/PRE Command to
ACTV Command
Specify the number of minimum cycles from the start of auto-
precharge or issuing of PRE command to the issuing of
ACTV command for the same bank. The setting for areas 2
and 3 is common.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
Reserved
This bit is always read as 0. The write value should always be
0.
Reserved
These bits are always read as 0. The write value should
always be 0.
CAS Latency for Area 2
Specify the CAS latency for area 2.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
Reserved
These bits are always read as 0. The write value should
always be 0.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010

Related parts for HD6417720BP133BV