HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 762

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 21 Serial I/O with FIFO (SIOF)
Page 702 of 1414
Bit
7
6
5
4
3
2
1
0
Bit Name
RFWM2
RFWM1
RFWM0
RFUA4
RFUA3
RFUA2
RFUA1
RFUA0
Initial
Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R
R
R
Description
Receive FIFO Watermark
000: Issue a transfer request when 1 stage or more of the
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Issue a transfer request when 4 or more stages of
101: Issue a transfer request when 8 or more stages of
110: Issue a transfer request when 12 or more stages of
111: Issue a transfer request when 16 stages of the
•
•
Receive FIFO Usable Area
Indicate the number of words that can be transferred by
the CPU or DMAC as B'00000 (empty) to B'10000 (full).
A transfer request to the receive FIFO is issued by the
RDREQ bit in SISTR.
The receive FIFO is always used as 16 stages of the
FIFO regardless of these bit settings.
receive FIFO are valid.
the receive FIFO are valid.
the receive FIFO are valid.
the receive FIFO are valid.
receive FIFO are valid.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010