HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 1187

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
33.3
33.3.1
The flow from setting of break conditions to user break exception processing is described below:
1. The break addresses and corresponding ASID are set in the break address registers (BARA or
2. When the break conditions are satisfied, the UBC sends a user break request to the CPU and
3. The appropriate condition match flags (SCMFCA, SCMFDA, SCMFCB, and SCMFDB) can
4. There is a chance that the break set in channel A and the break set in channel B occur around
5. When selecting the I bus as the break condition, note the following:
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
BARB) and break ASID registers (BASRA or BASRB in CNN). The masked addresses are set
in the break address mask registers (BAMRA or BAMRB). The break data is set in the break
data register (BDRB). The masked data is set in the break data mask register (BDMRB). The
bus break conditions are set in the break bus cycle registers (BBRA or BBRB). Three groups
of BBRA or BBRB (L bus cycle/I bus cycle select, instruction fetch/data access select, and
read/write select) are each set. No user break will be generated if even one of these groups is
set with 00. The respective conditions are set in the bits of the break control register (BRCR).
Make sure to set all registers related to breaks before setting BBRA or BBRB.
sets the L bus condition match flag (SCMFCA or SCMFCB) and the I bus condition match
flag (SCMFDA or SCMFDB) for the appropriate channel. When the X/Y memory bus is
specified for channel B, SCMFCB is used for the condition match flag.
be used to check if the set conditions match or not. The matching of the conditions sets flags,
but they are not reset. 0 must first be written to them before they can be used again.
the same time. In this case, there will be only one break request to the CPU, but these two
break channel match flags could be both set.
⎯ Several bus masters, including the CPU and DMAC, are connected to the I bus. The UBC
⎯ Physical addresses are used for the I bus. Set a physical address in break address registers
⎯ For data access cycles issued on the L bus by the CPU, if their virtual addresses are not to
⎯ For instruction fetch cycles issued on the L bus by the CPU, even though their virtual
monitors bus cycles generated by all bus masters, and determines the condition match.
(BARA and BARB). The bus cycles for virtual addresses issued on the L bus by the CPU
are converted to physical addresses before being output to the I bus. (If the address
translation function is enabled, address translation by the MMU is carried out.)
be cached, they are issued with the data size specified on the L bus and their addresses are
not rounded.
addresses are not to be cached, they are issued in longwords and their addresses are
rounded to match longword boundaries.
Operation
Flow of the User Break Operation
Section 33 User Break Controller (UBC)
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