HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 747

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
9
8
7 to 2
Bit Name
TXE
RXE
⎯
Initial
Value
All 0
0
0
R/W
R
R/W
R/W
Description
Transmit Enable
0: Disables data transmission from the SIOFTxD pin
1: Enables data transmission from the SIOFTxD pin
•
•
•
This bit is initialized in module stop mode.
Receive Enable
0: Disables data reception from SIOFRxD
1: Enables data reception from SIOFRxD
•
•
•
This bit is initialized in module stop mode.
Reserved
These bits are always read as 0. The write value should
always be 0.
This bit setting becomes valid at the start of the next
frame (at the rising edge of the SIOFSYNC signal).
When the 1 setting for this bit becomes valid, the
SIOF issues a transmit transfer request according to
the setting of the TFWM bit in SIFCTR. When
transmit data is stored in the transmit FIFO,
transmission of data from the SIOFTxD pin begins.
This bit is initialized upon a transmit reset.
This bit setting becomes valid at the start of the next
frame (at the rising edge of the SIOFSYNC signal).
When the 1 setting for this bit becomes valid, the
SIOF begins the reception of data from the
SIOFRxD pin. When receive data is stored in the
receive FIFO, the SIOF issues a reception transfer
request according to the setting of the RFWM bit in
SIFCTR.
This bit is initialized upon receive reset.
Section 21 Serial I/O with FIFO (SIOF)
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