HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 957

Manufacturer Part Number

HD6417720BP133BV

SH3-DSP, WITH USB AND LCDC, PB-F

Manufacturer

Renesas Electronics America

SuperH® SH7700r

Core Processor

Connectivity

FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB

DMA, LCD, POR, WDT

Number Of I /o

Program Memory Type

Voltage - Supply (vcc/vdd)

1.4 V ~ 1.6 V

Data Converters

A/D 4x10b; D/A 2x8b

Oscillator Type

Operating Temperature

-20°C ~ 75°C

Package / Case

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Program Memory Size

SH7720 Group, SH7721 Group

This LCDC is capable of controlling displays with up to 1024 × 1024 dots and 16 bpp (bits per

pixel). The image data for display is stored in VRAM, which is shared with the CPU. This LCDC

should read the data from VRAM before display.

This LSI has a maximum 32-burst memory read operation and a 2.4-kbyte line buffer, so although

a complete breakdown of the display is unlikely, there may be some problems with the display

depending on the combination. A recommended size at the frame rate of 60 Hz is 320 × 240 dots

in 16 bpp or 640 × 480 dots in 8 bpp.

As a rough standard, the bus occupation ratio shown below should not exceed 40%.

The overhead coefficient becomes 1.375 when the CL2 SDRAM is connected to a 32-bit data bus

and 1.188 when connected to a 16-bit data bus.

R01UH0083EJ0400 Rev. 4.00

Sep 21, 2010

Bus occupation ratio (%) =

LCD Module Sizes which can be Displayed in this LCDC

Overhead coefficient x Total number of display pixels ((HDCN + 1) x 8 x (VDLN + 1))

x Frame rate (Hz) x Number of colors (bpp)

CKIO (Hz) x Bus width (bit)

Section 26 LCD Controller (LCDC)

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