HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 336

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Interrupt Controller (INTC)
8.5
8.5.1
The sequence of interrupt operations is described below. Figure 8.3 is a flowchart of the
operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent,
3. The priority level of the interrupt selected by the interrupt controller is compared with the
4. Detection timing: The INTC operates, and notifies the CPU of interrupt requests, in
5. The interrupt source code is set in the interrupt event registers (INTEVT and INTEVT2).
6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively.
7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1.
8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the
Notes: 1. The interrupt mask bits (I3 to I0) in the status register (SR) are not changed by
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following the priority levels set in the interrupt priority registers A to J (IPRA to IPRJ). Lower
priority interrupts are held pending. If two of these interrupts have the same priority level or if
multiple interrupts occur within a single module, the interrupt with the highest priority is
selected, according to table 8.3, Interrupt Exception Handling Sources and Priority (IRQ
Mode) and table 8.4, Interrupt Exception Handling Sources and Priority (IRL Mode).
interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the request priority level
is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends
an interrupt request signal to the CPU.
synchronization with the peripheral clock (Pφ). The CPU receives an interrupt at a break in
instructions.
vector base register (VBR) and H'00000600). This jump is not a delayed branch. The interrupt
handler may branch with the INTEVT or INTEVT2 value as its offset in order to identify the
interrupt source. This enables it to branch to the handling routine for the individual interrupt
source.
2. The interrupt source flag should be cleared in the interrupt handler. To ensure that an
Operation
Interrupt Sequence
acceptance of an interrupt in this LSI.
interrupt source that should have been cleared is not inadvertently accepted again, read
the interrupt source flag after it has been cleared, and then clear the BL bit or execute
an RTE instruction.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010