HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 717

SH3-DSP, WITH USB AND LCDC, PB-F

HD6417720BP133BV

Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417720BP133BV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
SH7720 Group, SH7721 Group
20.3.5
ICSR performs confirmation of interrupt request flags and status.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
7
6
5
Bit Name
TDRE
TEND
RDRF
I
2
C Bus Status Register (ICSR)
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Transmit Data Register Empty
Description
[Setting condition]
[Clearing conditions]
Transmit End
[Setting conditions]
[Clearing conditions]
Receive Data Register Full
[Setting condition]
[Clearing conditions]
When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
When TRS is set
When a start condition (including re-transfer) has
been issued
When transmit mode is entered from receive mode in
slave mode
When 0 is written in TDRE after reading TDRE = 1
When data is written to ICDRT with an instruction
When the ninth clock of SCL rises with the I
format while the TDRE flag is 1
When 0 is written in TEND after reading TEND = 1
When data is written to ICDRT with an instruction
When a receive data is transferred from ICDRS to
ICDRR
When 0 is written in RDRF after reading RDRF = 1
When ICDRR is read with an instruction
Section 20 I
2
C Bus Interface (IIC)
Page 657 of 1414
2
C bus

Related parts for HD6417720BP133BV