MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 100

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

SRAM Operation
0-modulo-32K location in the 4-Gbyte address space and configured to respond to either
instruction or data accesses.Time-critical functions can be mapped into instruction the
system stack. Other heavily-referenced data can be mapped into memory.
The following summarizes features of the MCF5307 SRAM implementation:
4.3 SRAM Operation
The SRAM module provides a general-purpose memory block that the ColdFire processor
can access with single-cycle throughput. The location of the memory block can be specified
to any word-aligned address in the 4-Gbyte address space by RAMBAR[BA], described in
Section 4.4.1, “SRAM Base Address Register (RAMBAR).” The memory is ideal for
storing critical code or data structures or for use as the system stack. Because the SRAM
module connects physically to the processor’s high-speed local bus, it can service
processor-initiated accesses or memory-referencing debug module commands.
Instruction fetches and data reads can be sent to both the cache and SRAM blocks
simultaneously. If the reference is mapped into a region defined by the SRAM, the SRAM
provides data to the processor and any cache data is discarded. Data accessed from the
SRAM module are not cached.
Note also that the SRAM cannot be accessed by the on-chip DMAs. The on-chip system
configuration allows concurrent core and DMA execution, where the core can reference
code or data from the internal SRAM or cache while performing a DMA transfer.
4-2
• 4-Kbyte SRAM, organized as 1024 x 32 bits
• Single-cycle throughput. When the pipeline is full, one access can occur per clock
• Physical location on the processor’s high-speed local bus
• Memory location programmable on any 0-modulo-32K address boundary
• Byte, word, and longword address capabilities
• The RAM base address register (RAMBAR) defines the logical base address,
cycle.
attributes, and access types for the SRAM module.
Freescale Semiconductor, Inc.
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MCF5307 User’s Manual