MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 231

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 10-8 describes CSMR fields.
Reset
31–16
Field
Addr
R/W
.
Bits
5–1
8
7
6
0
31
Name
BAM
WP
SC,
UC,
AM
C/I,
SD,
UD
—
V
Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit
causes the corresponding CSAR bit to be ignored in the decode.
0 Corresponding address bit is used in chip-select decode.
1 Corresponding address bit is a don’t care in chip-select decode.
The block size for CS[7:0] is 2
So, if CSAR0 = 0x0000 and CSMR0[BAM] = 0x0008, CS0 would address two discontinuous
64-Kbyte memory blocks: one from 0x0000–0xFFFF and one from 0x8_0000–0x8_FFFF.
Likewise, for CS0 to access 32 Mbytes of address space starting at location 0x0, CS1 must begin
at the next byte after CS0 for a 16-Mbyte address space. Then CSAR0 = 0x0000,
CSMR0[BAM] = 0x01FF, CSAR1 = 0x0200, and CSMR1[BAM] = 0x00FF.
Write protect. Controls write accesses to the address range in the corresponding CSAR.
Attempting to write to the range of addresses for which CSARn[WP] = 1 results in the appropriate
chip select not being selected. No exception occurs.
0 Both read and write accesses are allowed.
1 Only read accesses are allowed.
Reserved, should be cleared.
Alternate master. When AM = 0 during an external master or DMA access, SC, SD, UC, and UD
are don’t cares in the chip-select decode.
Address space mask bits. These bits determine whether the specified accesses can occur to the
address space defined by the BAM for this chip select.
C/I
SC Supervisor code address space mask
SD Supervisor data address space mask
UC User code address space mask
UD User data address space mask
0 The address space assigned to this chip select. is available to the specified access type.
1 The address space assigned to this chip select. is not available (masked) to the specified access
Note that if if AM = 0, SC, SD, UC, and UD are ignored in the chip select decode on external
master or DMA access.
Valid bit. Indicates whether the corresponding CSAR, CSMR, and CSCR contents are valid.
Programmed chip selects do not assert until V is set (except for CS0, which acts as the global chip
select). Reset clears each CSMRn[V].
0 Chip select invalid
1 Chip select valid
type. If this address space is accessed, chip select is not activated and a regular external bus
cycle occurs.
Figure 10-3. Chip Select Mask Registers (CSMRn)
CPU space and interrupt acknowledge cycle mask
0x0B4 (CSMR4); 0x0C0 (CSMR5); 0x0CC (CSMR6); 0x0D8 (CSMR7)
0x084 (CSMR0); 0x090 (CSMR1); 0x09C (CSMR2); 0x0A8 (CSMR3);
BAM
Freescale Semiconductor, Inc.
Table 10-8. CSMRn Field Descriptions
For More Information On This Product,
Chapter 10. Chip-Select Module
Go to: www.freescale.com
n
; n = (number of bits set in respective CSMR[BAM]) + 16.
16 15
Unitialized
R/W
Description
—
9
WP — AM C/I SC SD UC UD V
8
7
6
Chip-Select Registers
5
4
3
2
1
10-7
0
0