MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 182

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Features
The following is a list of the key SIM features:
6-2
• Module base address register (MBAR)
• Phase-locked loop (PLL) clock control register (PLLCR) for CPU STOP instruction
• Interrupt controller
• Chip select module
• System protection and reset status
• Pin assignment register (PAR) configures the parallel port. See Section 6.2.9, “Pin
• Bus arbitration
— Base address location of all internal peripherals and SIM resources
— Address space masking to internal peripherals and SIM resources
— Control for turning off clocks to core and interrupt levels that turn clocks back on
Chapter 7, “Phase-Locked Loop (PLL).”
— Programmable interrupt level (1–7) for internal peripheral interrupts
— Programmable priority level (0–3) within each interrupt level
— Four external interrupts; one set to interrupt level 7; three others programmable
See Chapter 9, “Interrupt Controller.”
— Eight independent, user-programmable chip-select signals (CS[7:0]) that can
— Address masking for 64-Kbyte to 4-Gbyte memory block sizes
— Programmable wait states and port sizes
— External master access to chip selects
See Chapter 10, “Chip-Select Module.”
— Reset status indicating the cause of last reset
— Software watchdog timer with programmable secondary bus monitor
See Section 6.2.4, “Software Watchdog Timer.”
Assignment Register (PAR).”
— Default bus master park register (MPARK) controls internal and external bus
— Supports several arbitration algorithms
See Section 6.2.10, “Bus Arbitration Control.”
to two interrupt levels
interface with SRAM, PROM, EPROM, EEPROM, Flash, and peripherals
arbitration and enables display of internal accesses on the external bus for
debugging
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MCF5307 User’s Manual