MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 212

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MCF5307CFT66B

Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets

Specifications of MCF5307CFT66B

Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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I
8.5.5 I
In master-receive mode, reading the I2DR, Figure 8-9, allows a read to occur and initiates
next byte data receiving. In slave mode, the same function is available after it is addressed.
8.6 I
The following examples show programming for initialization, signalling START,
post-transfer software response, signalling STOP, and generating a repeated START.
8.6.1 Initialization Sequence
Before the interface can transfer serial data, registers must be initialized, as follows:
8.6.2 Generation of START
After completion of the initialization procedure, serial data can be transmitted by selecting
the master transmitter mode. On a multiple-master bus system, IBSR[IBB] must be tested
to determine whether the serial bus is free. If the bus is free (IBB = 0), the START signal
8-10
2
C Programming Examples
1. Set IFDR[IC] to obtain SCL frequency from the system bus clock. See
2. Update the IADR to define its slave address.
3. Set I2CR[IEN] to enable the I
4. Modify the I2CR to select master/slave mode, transmit/receive mode, and
Section 8.5.2, “I2C Frequency Divider Register (IFDR).”
interrupt-enable or not.
2
Address
C Programming Examples
2
Reset
Field
C Data I/O Register (I2DR)
R/W
If IBSR[IBB] when the I
following code sequence before proceeding with normal
initialization code. This issues a STOP command to the slave
device, placing it in idle state as if it were just power-cycled on.
I2CR = 0x0
I2CR = 0xA
dummy read of I2DR
IBSR = 0x0
I2CR = 0x0
7
Figure 8-9. I
Freescale Semiconductor, Inc.
For More Information On This Product,
6
Go to: www.freescale.com
MCF5307 User’s Manual
5
2
2
C bus interface system.
C Data I/O Register (I2DR)
2
C bus module is enabled, execute the
NOTE:
MBAR + 0x290
4
0000_0000
Read/Write
D
3
2
1
0

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