MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 62

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Features and Enhancements
2.1.1 Clock-Multiplied Microprocessor Core
The MCF5307 incorporates a clock-multiplying phase-locked loop (PLL). Increasing the
internal speed of the core also allows higher performance while providing the system
designer with an easy-to-use lower speed system interface.
The frequency of the processor complex can be 2x, 3x, or 4x the external bus speed.
The processor, cache, integrated SRAM, and misalignment module operate at the higher
speed clock (PCLK); other system integrated modules operate at the speed of the bus clock
(BCLKO). When combined with the enhanced pipeline structure of the Version 3 ColdFire
core, the processor and its local memories provide a high level of performance for today’s
demanding embedded applications.
PCLK can be disabled to minimize dissipation when a low-power mode is entered. This is
described in Section 7.2.3, “Reduced-Power Mode.”
2.1.2 Enhanced Pipelines
The IFP prefetches instructions. The OEP decodes instructions, fetches required operands,
then executes the specified function. The two independent, decoupled pipeline structures
maximize performance while minimizing core size. Pipeline stages are shown in Figure 2-1
and are summarized as follows:
2-22
• Four-stage IFP (plus optional instruction buffer stage)
• Two-stage OEP
— Instruction address generation (IAG) calculates the next prefetch address.
— Instruction fetch cycle 1 (IC1) initiates prefetch on the processor’s local
— Instruction fetch cycle 2 (IC2) completes prefetch on the processor’s instruction
— Instruction early decode (IED) generates time-critical decode signals needed for
— Instruction buffer (IB) optional stage uses FIFO queue to minimize effects of
— Decode, select/operand fetch (DSOC) decodes the instruction and selects the
— Address generation/execute (AGEX) Calculates the oeprand address, or
instruction bus.
local bus.
the OEP.
fetch latency.
required components for the effective address calculation, or the operand fetch
cycle.
performs the execution of the instruction.
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MCF5307 User’s Manual