MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 440

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

1
2
3
4
5
6
7
8
Input/Output AC Timing Specifications
Table 20-6 lists specifications for timings in Figure 20-3, Figure 20-4, and Figure 20-10.
Although output signals that share a specification number have approximately the same
timing, due to loading differences, they do not necessarily change at the same time.
However, they have similar timings; that is, minimum and maximum times are not mixed.
Note that these figures show two representative bus operations and do not attempt to show
all cases. For explanations of the states, S0–S5, see Section 18.4, “Data Transfer
20-4
B10
B11
B11a
B12
B13
B14
B15
B16
H1
H2
Outputs that only change on rising edge of BCLKO: RSTO, TS, BR, BD, TA, R/W, SIZ[1:0], PP[7:0] (and
PP[15:8] when configured as parallel port outputs).
Outputs that can change on either BCLKO edge depending only upon EDGESEL: D[31:0], A[23:0], SCKE,
SRAS, SCAS, DRAMW (and PP[15:8] when individually configured as address outputs).
Outputs that can change on either BCLKO edge depending only upon EDGESEL: D[31:0], A[23:0], SCKE,
SRAS, SCAS, DRAMW (and PP[15:8] when individually configured as address outputs).
Applies to D[31:0], A[23:0], RSTO, TS, BR, BD, TA, R/W, SIZ[1:0], PP[7:0] (and PP[15:8] when configured as
parallel port outputs).
Applies to RAS[1:0], CAS[1:0], SCKE, SRAS, SCAS, DRAMW
High Impedance (three-state): D[31:0]
Outputs that transition to high-impedance due to bus arbitration: A[23:0], R/W, SIZ[1:0], TS, AS, TA, (and
PP[15:0] when individually configured as address outputs)
Outputs that only change on falling edge of BCLKO: AS, CS[7:0], BE[3:0], OE
1
2
3
Num
B5
B6
Num
2,3
2,3
1,2,3
1,2,3,4
6,7
8,2,3
8,2,3
1,2,3,5
Inputs: BG, TA, A[23:0], PP[15:0], SIZ[1:0], R/W, TS, EDGESEL, D[31:0], IRQ[7,5,3,1], and BKPT
Inputs: AS
Inputs: D[31:0]
3
BCLKO to input high impedance
BCLKO to EDGESEL delay
BCLKO rising to valid
BCLKO rising to invalid (hold)
BCLKO rising to invalid (hold)
BCLKO to high impedance (three-state)
BCLKO rising to valid
BCLKO rising to invalid (hold)
EDGESEL to valid
EDGESEL to invalid (hold)
HIZ to high impedance
HIZ to low Impedance
Characteristic
Table 20-6. Output AC Timing Specification
Characteristic
Table 20-5. Input AC Timing Specification
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MCF5307 User’s Manual
Min
Min
0.5
—
—
—
—
—
—
—
0
1
3
3
66 MHz
66 MHz
Max
7.5
Max
18.5
2
15
—
—
15
15
—
—
60
60
Min
—
0
90 MHz
Min
0.5
—
—
—
—
—
—
1
2
2
90 MHz
Max
5.5
2
Max
13.5
11
11
11
60
60
—
—
—
—
Bus clock
Units
nS
Units
nS
nS
nS
nS
nS
nS
nS
nS
nS