MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 71

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MCF5307CFT66B

Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets

Specifications of MCF5307CFT66B

Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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2.2.2.4 Access Control Registers (ACR0–ACR1)
The access control registers (ACR0–ACR1) define attributes for two user-defined memory
regions. Attributes include definition of cache mode, write protect and buffer write enables.
See Section 4.10.2, “Access Control Registers (ACR0–ACR1).”
2.2.2.5 RAM Base Address Register (RAMBAR)
The RAMBAR register determines the base address location of the internal SRAM module
and indicates the types of references mapped to it. The RAMBAR includes a base address,
write-protect bit, address space mask bits, and an enable. The RAM base address must be
aligned on a 0-modulo-32-Kbyte boundary. See Section 4.4.1, “SRAM Base Address
Register (RAMBAR).”
2.2.2.6 Module Base Address Register (MBAR)
The module base address register (MBAR) defines the logical base address for the
memory-mapped space containing the control registers for the on-chip peripherals. See
Section 6.2.2, “Module Base Address Register (MBAR).”
2.3 Integer Data Formats
Table 2-4 lists the integer operand data formats. Integer operands can reside in registers,
memory, or instructions. The operand size for each instruction is either explicitly encoded
in the instruction or implicitly defined by the instruction operation.
2.4 Organization of Data in Registers
The following sections describe data organization within the data, address, and control
registers.
2.4.1 Organization of Integer Data Formats in Registers
Figure 2-7 shows the integer format for data registers. Each integer data register is 32 bits
wide. Byte and word operands occupy the lower 8- and 16-bit portions of integer data
registers, respectively. Longword operands occupy the entire 32 bits of integer data
registers. A data register that is either a source or destination operand only uses or changes
the appropriate lower 8 or 16 bits in byte or word operations, respectively. The remaining
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 2-4. Integer Data Formats
Bit
Byte integer
Word integer
Longword integer
Operand Data Format
Chapter 2. ColdFire Core
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16 bits
32 bits
8 bits
Size
1 bit
Integer Data Formats
2-31

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