MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 301

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Freescale Semiconductor, Inc.
General-Purpose Timer Programming Model
BCLKO is assumed to be the clock source. TIN cannot simultaneously function as a
clocking source and as an input capture pin.
15
0
Field
CAP (16-bit capture counter value)
Reset
0000_0000_0000_0000
R/W
Read only
Address
MBAR + 0x148 (TCR0); + 0x188 (TCR1)
Figure 13-4. Timer Capture Register (TCR0/TCR1)
13.3.4 Timer Counters (TCN0/TCN1)
The current value of the 16-bit, incrementing timer counters (TCN0/TCN1), Figure 13-5,
can be read anytime without affecting counting. Writing to TCNn clears it. The timer
counter decrements on the clock source rising edge (BCLKO ÷ 1, BCLKO ÷ 16, or TIN).
15
0
Field
16-bit timer counter value count
Reset
0000_0000_0000_0000
R/W
R/W (to reset)
Address
MBAR + 0x14C (TCN0); + 0x18C (TCN1)
Figure 13-5. Timer Counters (TCN0/TCN1)
13.3.5 Timer Event Registers (TER0/TER1)
Each timer event register (TER0/TER1), Figure 13-6, reports capture or reference events
events the timer recognizes by setting TERn[CAP] or TERn[REF], which it does regardless
of the corresponding interrupt-enable bit values, TMRn[ORI,CE].
Writing a 1 to either REF or CAP clears it (writing a 0 does not affect bit value); both bits
can be cleared at the same time. REF and CAP must be cleared early in the exception
handler, before the timer negates the IRQn to the interrupt controller.
7
2
1
0
Field
—
REF
CAP
Reset
0000_0000
R/W
R/W (ones clear/zeros have no effect)
Address
MBAR + 0x151 (TER0); + 0x191 (TER1)
Figure 13-6. Timer Event Registers (TER0/TER1)
Chapter 13. Timer Module
13-5
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