MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 384
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MCF5307CFT66B
Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307CFT66B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5307CFT66B
Manufacturer:
FREESCAL
Quantity:
154
Company:
Part Number:
MCF5307CFT66B
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Debug and Test Signals
17.13 Debug and Test Signals
The signals in this section interface with external I/O to provide processor status signals.
17.13.1 Test Mode (MTMOD[3:0])
The test mode signals choose between multiplexed debug module and JTAG signals. If
MTMOD0 is low, the part is in normal and background debug mode (BDM); if it is high,
it is in normal and JTAG mode. All other MTMOD values are reserved; MTMOD[3:1]
should be tied to ground and MTMOD[3:0] should not be changed while RSTI is negated.
17.13.2 High Impedance (HIZ)
The assertion of HIZ forces all output drivers to high-impedance state. The timing on HIZ
is independent of the clock. Note that HIZ does not override the JTAG operation;
TDO/DSO can be forced to high impedance by asserting TRST.
17.13.3 Processor Clock Output (PSTCLK)
The internal PLL generates this output signal, and is the processor clock output that is used
as the timing reference for the debug bus timing (DDATA[3:0] and PST[3:0]). PSTCLK is
at the same frequency as the core processor and cache memory. The frequency is 2x the
CLKIN.
17.13.4 Debug Data (DDATA[3:0])
The debug data signals (DDATA[3:0]) display captured processor data and breakpoint
status. See Chapter 5, “Debug Support,” for additional information on this bus.
17.13.5 Processor Status (PST[3:0])
The processor status pins indicate the MCF5307 processor status. During debug mode, the
timing is synchronous with the processor clock (PSTCLK) and the status is not related to
the current bus transfer. Table 2-11 shows the encodings of these signals.
17-20
MCF5307 User’s Manual
For More Information On This Product,
Go to: www.freescale.com
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