MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 237

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

11.2 DRAM Controller Operation
The DRAM controller mode is programmed through DCR[SO]. Asynchronous mode
(SO = 0) includes support for page mode and EDO DRAMs. Synchronous mode is
designed to work with industry-standard SDRAMs. These modes act very differently from
one another, especially regarding the use of DRAM registers and pins. Memory blocks
cannot operate in different modes; both are either synchronous or asynchronous.
11.2.1 DRAM Controller Registers
The DRAM controller registers memory map, Table 11-1, is the same regardless of whether
asynchronous or synchronous DRAM is used, although bit configurations may vary.
MBAR
Offset
0x10C
0x100
0x104
0x108
0x110
0x114
• Control logic and state machine—Generates all DRAM signals, taking bus cycle
• Hit logic—Compares address and attribute signals of a current DRAM bus cycle to
• Page hit logic—Determines if the next DRAM access is in the same DRAM page as
• Address multiplexing—Multiplexes addresses to allow column and row addresses
characteristic data from the block logic, along with hit information to generate
DRAM accesses. Handles refresh requests from the refresh counter.
— DRAM control register (DCR)—Contains data to control refresh operation of
— Refresh counter—Determines when refresh should occur, determined by the
both DACRs to determine if a DRAM block is being accessed. Hits are passed to the
control logic along with characteristics of the bus cycle to be generated.
the previous one. This information is passed on to the control logic.
to share pins. This allows glueless interface to DRAMs.
the DRAM controller. Both memory blocks are refreshed concurrently as
controlled by DCR[RC].
value of DCR[RC]. It generates a refresh request to the control block.
External masters cannot access MCF5307 on-chip memories or
MBAR, but they can access DRAM controller registers.
DRAM control register (DCR) [p. 11-4]
[31:24]
Chapter 11. Synchronous/Asynchronous DRAM Controller Module
Freescale Semiconductor, Inc.
Table 11-1. DRAM Controller Registers
For More Information On This Product,
DRAM address and control register 0 (DACR0) [p. 11-5]
DRAM address and control register 1 (DACR1) [p. 11-5]
DRAM mask register block 0 (DMR0) [p. 11-7]
DRAM mask register block 1 (DMR1) [p. 11-7]
Go to: www.freescale.com
[23:16]
NOTE:
Reserved
[15:8]
DRAM Controller Operation
Reserved
[7:0]
11-3