MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 397

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

The write cycle timing diagram is shown in Figure 18-8.
Table 18-4 describes the six states of a basic write cycle.
18.4.5 Fast-Termination Cycles
Two clock-cycle transfers are supported on the MCF5307 bus. In most cases, this is
impractical to use in a system because the termination must take place in the same half
clock during which AS is asserted. Because this is atypical, it is not referred to as the
zero-wait-state case but is called the fast-termination case. A fast-termination cycle is one
in which an external device or memory asserts TA as soon as TS is detected. This means
that the MCF5307 samples TA on the rising edge of the second cycle of the bus transfer.
Figure 18-9 shows a read cycle with fast termination. Note that fast termination cannot be
used with internal termination.
TM[2:0], SIZ[1:0]
A[31:0], TT[1:0]
1.
2.
3.
4.
5.
6.
7.
1.
1.
2.
AS, CSx
BCLKO
Set R/W to write
Place address on A[31:0]
Assert TT[1:0], TM[2:0], TIP,
and SIZ[1:0]
Assert TS
Assert AS
Place data on D[31:0]
Negate TS
Sample TA low
Tree-state D[31:0]
Start next cycle
D[31:0]
BWEx
R/W
TIP
TS
TA
MCF5307
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 18-8. Basic Write Bus Cycle
Figure 18-7. Write Cycle Flowchart
Chapter 18. Bus Operation
Go to: www.freescale.com
S0
S1
S2
Write
1.
2.
3.
1.
S3
Decode address
Store data on D[31:0]
Assert TA
Negate TA
S4
System
Data Transfer Operation
S5
18-9