MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 451

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

1
2
3
20.7 I
Table 20-10 lists specifications for the I
Table 20-11 lists specifications for the I
I1
I2
I3
I4
I5
I6
I7
I8
I9
I1
I2
I3
I4
I5
I6
I7
I8
I9
Num
Num
1
Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in Table 20-11. The I
designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed into the IFDR; however, the numbers given
in Table 20-11 are minimum values.
Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time
SCL or SDA take to reach a high level depends on external signal capacitance and pull-up resistor values.
Specified at a nominal 50-pF load.
1
2
1
3
1
1
1
1
Table 20-11. I
Start condition hold time
Clock low period
SCL/SDA rise time (V
Data hold time
SCL/SDA fall time (V
Clock high time
Data setup time
Start condition setup time (for repeated start condition only)
Stop condition setup time
Start condition hold time
Clock low period
SCL/SDA rise time (V
Data hold time
SCL/SDA fall time (V
Clock high time
Data setup time
Start condition setup time (for repeated start
condition only)
Stop condition setup time
Table 20-10. I
2
C Input/Output Timing Specifications
Characteristic
2
2
C Output Timing Specifications between SCL and SDA
IH
IH
Freescale Semiconductor, Inc.
C Input Timing Specifications between SCL and SDA
IL
IL
Characteristic
= 2.4 V to V
= 2.4 V to V
= 0.5 V to V
= 0.5 V to V
For More Information On This Product,
Chapter 20. Electrical Specifications
Go to: www.freescale.com
IL
IL
IH
IH
= 0.5 V)
= 0.5 V)
= 2.4 V)
= 2.4 V)
2
2
C output timing parameters shown in Figure 20.8.
C input timing parameters shown in Figure 20.8.
Min
10
10
20
10
—
—
6
7
2
66 MHz
Min
I
2
—
—
Max
2
8
0
4
0
2
2
C Input/Output Timing Specifications
—
—
—
—
—
—
—
—
66 MHz
3
Max
—
—
—
—
—
—
—
1
1
Min
10
—
—
10
20
10
6
7
2
90 MHz
Min
—
—
2
8
0
4
0
2
2
90 MHz
2
C interface is
Max
—
—
—
—
—
—
—
—
3
Max
—
—
—
—
—
—
—
1
1
Bus clocks
Bus clocks
Bus clocks
Bus clocks
Bus clocks
Bus clocks
Bus clocks
Bus clocks
Bus clocks
Bus clocks
Bus clocks
Bus clocks
Units
Units
µS
nS
mS
mS
nS
nS
20-15