MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 72

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Organization of Data in Registers
high-order portion does not change. The least significant bit (lsb) of all integer sizes is zero,
the most-significant bit (msb) of a longword integer is 31, the msb of a word integer is 15,
and the msb of a byte integer is 7.
The instruction set encodings do not allow the use of address registers for byte-sized
operands. When an address register is a source operand, either the low-order word or the
entire longword operand is used, depending on the operation size. Word-length source
operands are sign-extended to 32 bits and then used in the operation with anaddress register
destination. When an address register is a destination, the entire register is affected,
regardless of the operation size. Figure 2-8 shows integer formats for address registers.
The size of control registers varies according to function. Some have undefined bits
reserved for future definition by Motorola. Those particular bits read as zeros and must be
written as zeros for future compatibility.
All operations to the SR and CCR are word-size operations. For all CCR operations, the
upper byte is read as all zeros and is ignored when written, regardless of privilege mode.
2.4.2 Organization of Integer Data Formats in Memory
All ColdFire processors use a big-endian addressing scheme. The byte-addressable
organization of memory allows lower addresses to correspond to higher order bytes. The
address N of a longword data item corresponds to the address of the high-order word. The
lower order word is located at address N + 2. The address N of a word data item corresponds
to the address of the high-order byte. The lower order byte is located at address N + 1. This
2-32
Figure 2-8. Organization of Integer Data Formats in Address Registers
msb
msb
31
31
31
31
31
31
Figure 2-7. Organization of Integer Data Formats in Data Registers
30
Not used
Not used
Sign-Extended
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msb
Full 32-Bit Address Operand
MCF5307 User’s Manual
15
msb Low order byte
7
Lower order word
16
15
1
16-Bit Address Operand
lsb
lsb
lsb
lsb
0
0
0
0
Bit (0 ≤ bit number ≤ 31)
Byte (8 bits)
Word (16 bits)
Longword (32 bits)
0
0