MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 337
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MCF5307CFT66B
Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307CFT66B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number:
MCF5307CFT66B
Manufacturer:
FREESCAL
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Part Number:
MCF5307CFT66B
Manufacturer:
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a slave receives a block of data, its CPU disables the receiver and repeats the
process.Functional timing information for multidrop mode is shown in Figure 14-26.
A character sent from the master station consists of a start bit, a programmed number of
data bits, an address/data (A/D) bit flag, and a programmed number of stop bits. A/D = 1
indicates an address character; A/D = 0 indicates a data character. The polarity of A/D is
selected through UMR1n[PT]. UMR1n should be programmed before enabling the
transmitter and loading the corresponding data bits into the transmit buffer.
In multidrop mode, the receiver continuously monitors the received data stream, regardless
of whether it is enabled or disabled. If the receiver is disabled, it sets the RxRDY bit and
loads the character into the receiver holding register FIFO stack provided the received A/D
bit is a one (address tag). The character is discarded if the received A/D bit is zero (data
tag). If the receiver is enabled, all received characters are transferred to the CPU through
the receiver holding register stack during read operations.
In either case, the data bits are loaded into the data portion of the stack while the A/D bit is
loaded into the status portion of the stack normally used for a parity error (USRn[PE]).
Framing error, overrun error, and break detection operate normally. The A/D bit takes the
place of the parity bit; therefore, parity is neither calculated nor checked. Messages in this
USRn[RxRDY]
USRn[TxRDY]
Transmitter
Receiver
Enabled
Enabled
internal
module
internal
module
select
select
RxD
TxD
UMR1n[PM] = 11
UMR1n[PT] = 1
UMR1n
UMR1n[PM] = 11
Figure 14-26. Multidrop Mode Timing Diagram
[PM] = 11
Freescale Semiconductor, Inc.
A/D
ADD 1
For More Information On This Product,
0
UMR1n[PT] = 0
ADD1
ADD1
Chapter 14. UART Modules
A/D
A/D
Go to: www.freescale.com
C0
1
1
ADD 1
Peripheral Station
C0
C0
Master Station
A/D
A/D
Status Data
UMR1n[PT] = 2
(C0)
ADD 2
ADD2
ADD2
A/D
A/D
1
1
Status Data
(ADD 2)
A/D
0
Operation
14-27
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