MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 194

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Programming Model
6.2.10.1.2 Arbitration between Internal and External Masters for
If an external device is programmed to access internal MCF5307 resources
(EARBCTRL = 1), the external device can gain bus mastership only when BG is negated.
This means neither the core nor the DMA controller can access the external bus until the
external device asserts BG. After the external master finishes its bus transfer and asserts
BG, the core has priority on the next available bus cycle regardless of the value of PARK.
Thus if the core asserts its internal bus request on this first bus cycle, it executes a bus cycle
even if PARK indicates the DMA should have priority. Then, after the bus transfer, the
PARK scheme returns to programmed functioning and the DMA is given bus mastership.
6-14
• Park on current master priority (PARK = 11)—The current bus master retains
• In a single-master system, the setting of EARBCTRL does not affect arbitration
mastership as long as it needs the bus. The other device can become the bus master
only when the bus is idle. For example, if the core is bus master out of reset, it retains
mastership as long as it needs the bus. It loses mastership only when it negates its
bus request signal and the DMA asserts its internal bus request signal. At this point
the DMA module is the bus master, and retains bus mastership as long as it needs
the bus. See Figure 6-13.
performance. Typically, BG is tied low and the MCF5307 always owns the external
bus and internal register transfers are already shown on the external bus. In a system
where MCF5307 is the only master, this bit may remain cleared.
If the system needs external visibility of the data bus values during internal register
transfers for system debugging, both EARBCTRL and SHOWDATA must be set.
Note that when an internal register transfer is driven externally, TA becomes an
output, which is asserted (normally an input) to prevent external devices and
DMA module BR asserted
DMA module BR negated
Accessing Internal Resources
In all arbitration modes, if BG is negated, the external master
interface has highest priority. In this case, the ColdFire core has
second-highest priority, until the internal bus grant is asserted.
Figure 6-13. Park on Current Master Priority (PARK = 01)
Core BR asserted
Core BR negated
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DMA module BR asserted
MCF5307 User’s Manual
DMA module BR negated
Core BR negated
Core BR asserted
NOTE:
DMA Module
DMA module BR negated
Core BR negated
DMA module BR asserted
Core BR asserted