MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 236
MCF5307CFT66B
Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307CFT66B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MCF5307CFT66B
Manufacturer:
FREESCAL
Quantity:
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Company:
Part Number:
MCF5307CFT66B
Manufacturer:
Freescale Semiconductor
Quantity:
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Overview
11.1.1 Definitions
The following terminology is used in this chapter:
11.1.2 Block Diagram and Major Components
The basic components of the DRAM controller are shown in Figure 11-1.
The DRAM controller’s major components, shown in Figure 11-1, are described as
follows:
11-2
Internal
A[31:0]
• A/SDRAM block—Any group of DRAM memories selected by one of the
• SDRAM—RAMs that operate like asynchronous DRAMs but with a synchronous
• SDRAM bank—An internal partition in an SDRAM device. For example, a 64-Mbit
• DRAM address and control registers (DACR0 and DACR1)—The DRAM
Bus
Figure 11-1. Asynchronous/Synchronous DRAM Controller Block Diagram
MCF5307 RAS[1:0] signals. Thus, the MCF5307 can support two independent
memory blocks. The base address of each block is programmed in the DRAM
address and control registers (DACR0 and DACR1).
clock, a pipelined, multiple-bank architecture, and faster speed.
SDRAM component might be configured as four 512K x 32 banks. Banks are
selected through the SDRAM component’s bank select lines.
controller consists of two configuration register units, one for each supported
memory block. DACR0 is accessed at MBAR + 0x0108; DACR1 is accessed at
0x010. The register information is passed on to the hit logic.
DRAM Address/Control Register 0
DRAM Address/Control Register 1
Memory Block 0 Hit Logic
Memory Block 1 Hit Logic
Freescale Semiconductor, Inc.
Page Hit
(DACR0)
(DACR1)
For More Information On This Product,
Logic
DRAM Controller Module
Go to: www.freescale.com
MCF5307 User’s Manual
Refresh Counter
Register (DCR)
DRAM Control
State Machine
Control Logic
Multiplexing
Address
and
A[31:0]
RAS[1:0]
CAS[3:0]
DRAMW
SCAS
SRAS
SCKE
These signals
are used for
SDRAM only
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