MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 47

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Freescale Semiconductor, Inc.
ColdFire Module Description
1.3 ColdFire Module Description
The following sections provide overviews of the various modules incorporated in the
MCF5307.
1.3.1 ColdFire Core
The Version 4 ColdFire core consists of two independent and decoupled pipelines to
maximize performance—the instruction fetch pipeline (IFP) and the operand execution
pipeline (OEP).
1.3.1.1 Instruction Fetch Pipeline (IFP)
The four-stage instruction fetch pipeline (IFP) is designed to prefetch instructions for the
operand execution pipeline (OEP). Because the fetch and execution pipelines are decoupled
by a eight-instruction FIFO buffer, the fetch mechanism can prefetch instructions in
advance of their use by the OEP, thereby minimizing the time stalled waiting for
instructions. To maximize the performance of branch instructions, the Version 3 IFP
implements a branch prediction mechanism. Backward branches are predicted to be taken.
The prediction for forward branches is controlled by a bit in the Condition Code Register
(CCR). These predictions allow the IFP to redirect the fetch stream down the path predicted
to be taken well in advance of the actual instruction execution. The result is significantly
improved performance.
1.3.1.2 Operand Execution Pipeline (OEP)
The prefetched instruction stream is gated from the FIFO buffer into the two-stage OEP.
The OEP consists of a traditional two-stage RISC compute engine with a register file access
feeding an arithmetic/logic unit (ALU). The OEP decodes the instruction, fetches the
required operands and then executes the required function.
1.3.1.3 MAC Module
The MAC unit provides signal processing capabilities for the MCF5307 in a variety of
applications including digital audio and servo control. Integrated as an execution unit in the
processor’s OEP, the MAC unit implements a three-stage arithmetic pipeline optimized for
16 x 16 multiplies. Both 16- and 32-bit input operands are supported by this design in
addition to a full set of extensions for signed and unsigned integers, plus signed, fixed-point
fractional input operands.
1.3.1.4 Integer Divide Module
Integrated into the OEP, the divide module performs operations using signed and unsigned
integers. The module supports word and longword divides producing quotients and/or
remainders.
Chapter 1. Overview
1-7
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