MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 213

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

and the first byte (the slave address) can be sent. The data written to the data register
comprises the address of the desired slave and the lsb indicates the transfer direction.
The free time between a STOP and the next START condition is built into the hardware that
generates the START cycle. Depending on the relative frequencies of the system clock and
the SCL period, it may be necessary to wait until the I
address to the I2DR before proceeding with the following instructions.
The following example signals START and transmits the first byte of data (slave address):
CHFLAG
TXSTART MOVE.B I2CR,-(A0);Set transmit mode
IFREE
8.6.3 Post-Transfer Software Response
Sending or receiving a byte sets the I2SR[ICF], which indicates one byte communication
is finished. I2SR[IIF] is also set. An interrupt is generated if the interrupt function is
enabled during initialization by setting I2CR[IIEN]. Software must first clear IIF in the
interrupt routine. ICF is cleared either by reading from I2DR in receive mode or by writing
to I2DR in transmit mode.
Software can service the I
function is disabled. Polling should monitor IIF rather than ICF because that operation is
different when arbitration is lost.
When an interrupt occurs at the end of the address cycle, the master is always in transmit
mode; that is, the address is sent. If master receive mode is required (I2DR[R/W],
I2CR[MTX] should be toggled.
During slave-mode address cycles (I2SR[IAAS] = 1), I2SR[SRW] is read to determine the
direction of the next transfer. MTX is programmed accordingly. For slave-mode data cycles
(IAAS = 0), SRW is invalid. MTX should be read to determine the current transfer
direction.
The following is an example of a software response by a master transmitter in the interrupt
routine (see Figure 8-10).
I2SR
MOVE.B I2SR,-(A0);Check I2SR[MBB]
BTST.B #5, (A0)+
BNE.S CHFLAG;If I2SR[MBB] = 1, wait until it is clear
BSET.B #4,(A0)
MOVE.B (A0)+, I2CR
MOVE.B I2CR, -(A0);Set master mode
BSET.B #5, (A0);Generate START condition
MOVE.B (A0)+, I2CR
MOVE.B CALLING,-(A0);Transmit the calling address, D0=R/W
MOVE.B (A0)+, I2DR
MOVE.B I2SR,-(A0);Check I2SR[MBB]
BTST.B #5, (A0)+;
BEQ.S IFREE;
LEA.L I2SR,-(A7);Load effective address
BCLR.B #1,(A7)+;Clear the IIF flag
MOVE.B I2CR,-(A7);Push the address on stack,
;If it is clear, wait until it is set.
Freescale Semiconductor, Inc.
For More Information On This Product,
2
C I/O in the main program by monitoring IIF if the interrupt
Go to: www.freescale.com
Chapter 8. I
2
C Module
2
C is busy after writing the calling
I
2
C Programming Examples
8-11