MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 166
MCF5307CFT66B
Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307CFT66B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Quantity
Price
Company:
Part Number:
MCF5307CFT66B
Manufacturer:
FREESCAL
Quantity:
154
Company:
Part Number:
MCF5307CFT66B
Manufacturer:
Freescale Semiconductor
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Background Debug Mode (BDM)
5.5.3.3.12 Read Debug Module Register (
Read the selected debug module register and return the 32-bit result. The only valid register
selection for the
clears the trigger status bits (CSR[BSTAT]) if either a level-2 breakpoint has been triggered
or a level-1 breakpoint has been triggered and no level-2 breakpoint has been enabled.
Command/Result Formats:
Table 5-20 shows the definition of DRc encoding.
Command Sequence:
Operand Data:
Result Data:
5-38
1
Command
0x01–0x1F
DRc[4:0]
Note 0x4 is a 3-bit field
0x00
Result
15
Figure 5-40.
RDMREG
14
Debug Register Definition
0x2
Table 5-20. Definition of DRc Encoding—Read
Configuration/Status
None
The contents of the selected debug register are returned as a
longword value. The data is returned most-significant word first.
13
Figure 5-41.
Freescale Semiconductor, Inc.
For More Information On This Product,
Reserved
command is CSR (DRc = 0x00). Note that this read of the CSR
RDMREG
12
???
RDMREG BDM
11
Go to: www.freescale.com
MCF5307 User’s Manual
RDMREG
10
0xD
9
MS RESULT
"ILLEGAL"
Command/Result Formats
Command Sequence
XXX
XXX
D[31:16]
8
D[15:0]
Mnemonic
RDMREG
7
CSR
—
0x4
"NOT READY"
6
LS RESULT
NEXT CMD
NEXT CMD
1
)
5
Initial State
4
0x0
—
3
DRc
2
1
p. 5-10
Page
—
0
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