MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 222

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Interrupt Controller Registers
Table 9-5 describes AVR fields.
Table 9-6 shows the correlation between AVR[AVEC] and the external interrupts. Note that
an AVECn bit is valid only when the corresponding external interrupt request level is
enabled in the IRQPAR.
9.2.3 Interrupt Pending and Mask Registers (IPR and IMR)
The interrupt pending register (IPR), Figure 9-4, makes visible the interrupt sources that
have an interrupt pending. The interrupt mask register (IMR), also shown in Figure 9-4, is
used to mask the internal and external interrupt sources.
An interrupt is masked by setting, and enabled by clearing, the corresponding IMR bit.
When a masked interrupt occurs, the corresponding IPR bit is still set, but no interrupt
request is passed to the core.
9-6
7–1
.
Bit
0
Autovector Interrupt Source
External interrupt request 1
External interrupt request 2
External interrupt request 3
External interrupt request 4
External interrupt request 5
External interrupt request 6
External interrupt request 7
Name
AVEC Autovector control. Determines whether the external interrupt at that level is autovectored.
BLK
0 Interrupting source returns vector during interrupt-acknowledge cycle.
1 SIM generates autovector during interrupt-acknowledge cycle.
Block address strobe (AS) for external AVEC access. Available for users who use AS as a global
chip select for peripherals and do not want to enable them during an AVEC cycle.
0 Do not block address strobe.
1 Block address strobe from asserting.
To mask interrupt sources, first set the core’s status register
interrupt mask level to that of the source being masked in the
IMR. Then, the IMR bit can be masked.
Table 9-6. Autovector Register Bit Assignments
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 9-5. AVR Field Descriptions
Go to: www.freescale.com
MCF5307 User’s Manual
Autovector Register Bit Location
NOTE:
AVEC1
AVEC2
AVEC3
AVEC4
AVEC5
AVEC6
AVEC7
Description
Vector Offset
0x6C
0x7C
0x64
0x68
0x70
0x74
0x78