MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 133

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bytes are displayed in least-to-most-significant order. The processor captures only those
target addresses associated with taken branches which use a variant addressing mode, that
is, RTE and RTS instructions, JMP and JSR instructions using address register indirect or
indexed addressing modes, and all exception vectors.
The simplest example of a branch instruction using a variant address is the compiled code
for a C language case statement. Typically, the evaluation of this statement uses the variable
of an expression as an index into a table of offsets, where each offset points to a unique case
within the structure. For such change-of-flow operations, the MCF5307 uses the debug pins
to output the following sequence of information on successive processor clock cycles:
Another example of a variant branch instruction would be a JMP (A0) instruction.
Figure 5-3 shows when the PST and DDATA outputs that indicate when a JMP (A0)
executed, assuming the CSR was programmed to display the lower 2 bytes of an address.
PST is driven with a 0x5 in the first cycle and 0x9 in the second. The 0x5 indicates a taken
branch and the marker value 0x9 indicates a 2-byte address. Thus, the 4 subsequent DDATA
nibbles display the lower 2 bytes of address register A0 in least-to-most-significant nibble
order. The PST output after the JMP instruction completes depends on the target
instruction. The PST can continue with the next instruction before the address has
completely displayed on DDATA because of the DDATA FIFO. If the FIFO is full and the
next instruction has captured values to display on DDATA, the pipeline stalls (PST = 0x0)
until space is available in the FIFO.
5.4 Programming Model
In addition to the existing BDM commands that provide access to the processor’s registers
and the memory subsystem, the debug module contains nine registers to support the
required functionality. These registers are also accessible from the processor’s supervisor
PSTCLK
DDATA
1. Use PST (0x5) to identify that a taken branch was executed.
2. Using the PST pins, optionally signal the target address to be displayed sequentially
3. The new target address is optionally available on subsequent cycles using the
PST
on the DDATA pins. Encodings 0x9–0xB identify the number of bytes displayed.
DDATA port. The number of bytes of the target address displayed on this port is
configurable (2, 3, or 4 bytes).
Figure 5-3. Example JMP Instruction Output on PST/DDATA
0x5
0x0
Freescale Semiconductor, Inc.
For More Information On This Product,
0x9
0x0
Chapter 5. Debug Support
Go to: www.freescale.com
A[3:0]
A[7:4]
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Programming Model
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