MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 477
MCF5307CFT66B
Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307CFT66B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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M
MAC
Mask registers
MBAR, 6-4
Mechanical data
Memory SIM register, 6-3
MOVEC instruction, 5-36
O
Output port command registers, 14-15
P
Parallel port
Pin assignment register, 6-10, 15-1
PLL, 7-2
Power supply filter circuit, 7-6
Privilege level modes, 1-12
Programming models
signal descriptions, 19-2
TAP controller, 19-3
test logic disabling, 19-11
data representation, 3-4
instruction execution timings, 3-5
instruction set summary, 3-4
operation, 3-3
programming model, 2-26, 3-2
status register (MACSR), 1-14, 2-29
DRAM, 11-7, 11-22
MAC, 1-14, 2-29
case drawing, 16-9
diagram, 16-8
pinout, 16-1
code example, 15-3
data direction register, 15-2
data register, 15-2
operation, 15-1
clock control for STOP, 6-10
clock frequency relationships, 7-4
control register, 7-3
modes, 7-2
operation, 7-2
overview, 7-1
port list, 7-3
power supply filter circuit, 7-6
reset/initialization, 7-2
timing relationships, 7-4
overview, 2-26
SIM, 6-3
summary, A-1
supervisor, 2-29
user, 2-27
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INDEX
Index
PST outputs, 5-3
PULSE instruction, 5-4
R
Registers
ABLR/ABHR, 5-7, 5-8
address (A0 – A6), 2-27
AVR, 9-5
BDM address attribute, 5-9
bus master park, 6-11
chip-select
condition code, 2-28
condition code (CCR), 2-28
data breakpoint/mask, 5-12
data D0 - D7, 2-27
DBR/DBMR, 5-7
debug attribute trigger, 5-7
DMA
DRAM
I
I2CR, 8-8
I2DR, 8-10
I2SR, 8-9
IADR, 8-6
IFDR, 8-7
interrupt controller
IPR and IMR, 9-6
IRQPAR, 9-7
JTAG
2
C
control, 10-8
mask, 10-6
module, 10-5
byte count, 12-7
source address, 12-6
asynchronous
general operation, 11-3
synchronous
address, 8-6
control, 8-8
data I/O, 8-10
frequency divider, 8-7
status, 8-9
autovector, 9-5
pending and mask, 9-6
port assignment, 9-7
address and control, 11-5
DACR, 11-5
DCR, 11-4
DMR, 11-7
mode signals, 11-4
DACR, 11-20
DCR, 11-19
DMR, 11-22
mode settings, 11-33
Index-19
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