MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 243

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Note the following:
Table 11-7, Table 11-8, and Table 11-9 show how 8-, 16-, and 32-bit symmetrical ADRAM
memories are connected to the address bus. The memory sizes show what DRAM size is
accessed if the corresponding bits are connected to the memory. In each case, there is a base
memory size. This limitation exists to allow simple page-mode multiplexing. Notice also
that MCF5307 pin 17 is treated differently in byte-wide operations. In byte-wide
operations, address bits 16 and 17 are driven on MCF5307 physical address pins 16 and 17,
rather than the two bits being driven solely on A17, as they are for 32-wide memories.
Address Pin
• Each MCF5307 address bit drives both a row address and a column address bit.
• As the user upgrades ADRAM, corresponding MCF5307 address bits must be
• Some differences exist for each of the three possible port sizes. Note that only 8-bit
• If a 32-bit port is used with only eight column address lines, A18 must drive DRAM
• All ADRAM blocks have a fixed page size of 512 bytes for page-mode operation.
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connected. This multiplexing scheme allows various memory widths to be
connected to the address bus.
ports use an A0 address from the MCF5307. Because 16- and 32-bit ports issue
either words or longwords when accessed, they do not use the MCF5307 A0 signal.
Likewise, the configuration for 32-bit ports uses neither A0 or A1. This presents a
slight problem because DRAM address signal A0 is issued on physical pin A17 of
the MCF5307 along with the ADRAM address signal A17. Although A0 is not used
for larger ports, A17 is still needed. The MCF5307 DRAM controller provides for
this by changing the column address that appears on physical pin A17 of the
processor whenever an 8-bit port is not selected. This is determined by the
DACRn[PS] settings. For 8-bit ports, MCF5307 physical pin A17 drives logical
address A0 during the CAS cycle. When 16- or 32-bit port sizes are programmed,
the CAS cycle pin A17 drives logical address A16, as indicated in the generic
connection scheme.
address bit A18. Otherwise, in 32-bit port configurations, the MCF5307 physical
address line is not connected with more than eight column address lines.
The addresses are connected differently for various width combinations.
Table 11-6. Generic Address Multiplexing Scheme (Continued)
Row Address
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Chapter 11. Synchronous/Asynchronous DRAM Controller Module
Freescale Semiconductor, Inc.
For More Information On This Product,
Column Address
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Go to: www.freescale.com
Notes Relating to Port Sizes
Asynchronous Operation
11-9