MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 44
MCF5307CFT66B
Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307CFT66B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5307CFT66B
Manufacturer:
FREESCAL
Quantity:
154
Company:
Part Number:
MCF5307CFT66B
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MCF5307 Features
1.2 MCF5307 Features
The following list summarizes MCF5307 features:
1-4
• ColdFire processor core
• Multiply and accumulate unit (MAC)
• Hardware integer divide unit
• 8-Kbyte unified cache
• 4-Kbyte SRAM
— Variable-length RISC, clock-multiplied Version 3 microprocessor core
— Fully code compatible with Version 2 processors
— Two independent decoupled pipelines: four-stage instruction fetch pipeline (IFP)
— Eight-instruction FIFO buffer provides decoupling between the pipelines
— Branch prediction mechanisms for accelerating program execution
— 32-bit internal address bus supporting 4 Gbytes of linear address space
— 32-bit data bus
— 16 user-accessible, 32-bit-wide, general-purpose registers
— Supervisor/user modes for system protection
— Vector base register to relocate exception-vector table
— Optimized for high-level language constructs
— High-speed, complex arithmetic processing for DSP applications
— Tightly coupled to the OEP
— Three-stage execute pipeline with one clock issue rate for 16 x 16 operations
— 16 x 16 and 32 x 32 multiplies support, all with 32-bit accumulate
— Signed or unsigned integer support, plus signed fractional operands
— Unsigned and signed integer divide support
— Tightly coupled to the OEP
— 32/16 and 32/32 operation support producing quotient and/or remainder results
— Four-way set-associative organization
— Operates at higher processor core frequency
— Provides pipelined, single-cycle access to critical code and data
— Supports write-through and copyback modes
— Four-entry, 32-bit store buffer to improve performance of operand writes
— Programmable location anywhere within 4-Gbyte linear address space
— Higher core-frequency operation
— Pipelined, single-cycle access to critical code or data
and two-stage operand execution pipeline (OEP)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MCF5307 User’s Manual
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