MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 126

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MCF5307CFT66B

Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets

Specifications of MCF5307CFT66B

Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5307CFT66B
Manufacturer:
FREESCAL
Quantity:
154
Part Number:
MCF5307CFT66B
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Cache Operation Summary
The following tables present the same information as Table 4-6, organized by the current
state of the cache line. In Table 4-7 the current state is invalid.
In Table 4-8 the current state is valid.
4-28
Read miss
Read hit
Write miss (copyback)
Write miss (write-through)
Write hit (copyback)
Write hit (write-through)
Cache invalidate
Cache push
Cache push
Table 4-7. Cache Line State Transitions (Current State Invalid)
Read miss
Read hit
Write miss (copyback)
Write miss (write-through)
Write hit (copyback)
Write hit (write-through)
Cache invalidate
Cache push
Cache push
Table 4-8. Cache Line State Transitions (Current State Valid)
Access
Access
Freescale Semiconductor, Inc.
For More Information On This Product,
(C,W)V1 Read new line from memory and update cache;
(C,W)V2 Supply data to processor;
CV3
WV3
CV4
WV4
(C,W)V5 No action;
(C,W)V6 No action;
(C,W)V7 No action;
Go to: www.freescale.com
(C,W)I1 Read line from memory and update cache;
(C,W)I2 Not possible
CI3
WI3
CI4
WI4
(C,W)I5 No action;
(C,W)I6 No action;
(C,W)I7 No action;
MCF5307 User’s Manual
supply data to processor; stay in valid state.
stay in valid state.
Read new line from memory and update cache;
write data to cache;
go to modified state.
Write data to memory;
stay in valid state.
Write data to cache;
go to modified state.
Write data to memory and to cache;
stay in valid state.
go to invalid state.
go to invalid state.
stay in valid state.
supply data to processor;
go to valid state.
write data to cache;
go to modified state.
stay in invalid state.
stay in invalid state.
stay in invalid state.
stay in invalid state.
Read line from memory and update cache;
Write data to memory;
Not possible
Not possible
Response
Response

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