MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 271

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MCF5307CFT66B

Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets

Specifications of MCF5307CFT66B

Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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11.5.4 DMR Initialization
In this example, again, only the second 512-Kbyte block of each 1-Mbyte space is accessed
in each bank. In addition the SDRAM component is mapped only to readable and writable
supervisor and user data. The DMRs have the following configuration.
With this configuration, the DMR0 = 0x0074_0075, as described in Table 11-36.
31–16
15–9
8
7
6
5
4
3
2
1
0
2
1–0
Bits
Setting
Setting
Bits
(hex)
(hex)
Field
Field
Name
BAM
WP
AM
UC
UD
SC
SD
C/I
V
31
15
X
Name
0
PM
Setting
X
0
0
1
1
1
0
1
0
1
Setting
0
0
1
X
0
Chapter 11. Synchronous/Asynchronous DRAM Controller Module
With bits 17 and 16 as don’t cares, BAM = 0x0074, which leaves bank select bits and
upper 512K select bits unmasked. Note that bits 22 and 21 are set because they are used
as bank selects; bit 20 is set because it controls the 1-Mbyte boundary address.
Reserved. Don’t care.
Allow reads and writes
Reserved
Disable CPU space access
Disable alternate master access
Disable supervisor code accesses
Enable supervisor data accesses
Disable user code accesses
Enable user data accesses
Enable accesses.
Freescale Semiconductor, Inc.
Table 11-35. DACR Initialization Values
Table 11-36. DMR0 Initialization Values
Indicates continuous page mode
Reserved. Don’t care.
X
0
For More Information On This Product,
Figure 11-28. DMR0 Register
X
0
Go to: www.freescale.com
X
0
0
0
0
X
9
BAM
WP
0
0
8
X
0
7
Description
Description
C/I
1
1
6
7
7
AM
1
1
5
SC
1
1
4
SD
0
0
3
SDRAM Example
UC
18
1
1
2
4
5
UD
17
X
1
0
11-37
16
X
V
0
1

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