MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 373

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

= 01), a word is next transferred at offset 0x2 (SIZ[1:0] = 10), then the final byte is
transferred at offset 0x4 (SIZ[1:0] = 01).
For aligned transfers larger than the port size, SIZ[1:0] behaves as follows:
For burst-inhibited transfers, SIZ[1:0] changes with each TS assertion to reflect the next
transfer size. For transfers to port sizes smaller than the transfer size, SIZ[1:0] indicates the
size of the entire transfer on the first access and the size of the current port transfer on
subsequent transfers. For example, for a longword write to an 8-bit port, SIZ[1:0] = 00 for
the first byte transfer and 01 for the next three.
17.2.5 Transfer Start (TS)
The MCF5307 asserts TS during the first clock cycle when address and attributes (TM, TT,
TIP, R/W, and SIZ) are valid. TS is negated in the following clock cycle. When the
MCF5307 is not the bus master, TS is an input.
17.2.6 Address Strobe (AS)
Address strobe (AS) is asserted to indicate when the address is stable at the start of a bus
cycle. The address and attributes are guaranteed to be valid during the entire period that AS
is asserted. This signal is asserted and negated on the falling edge of the clock. When the
MCF5307 is not the bus master, AS is an input.
17.2.7 Transfer Acknowledge (TA)
When the MCF5307 is bus master, the external system drives this input to terminate the bus
transfer. The bus continues to be driven until this synchronous signal is asserted. For write
cycles, the processor continues to drive data one clock after TA is asserted. During read
cycles, the peripheral must continue to drive data until TA is recognized.
If all bus cycles support fast termination, TA can be tied low. However, note that TA cannot
be tied low if potential external bus masters are present. The MCF5307 drives TA for an
• If bursting is used, SIZ[1:0] stays at the size of transfer.
• If bursting is inhibited, SIZ[1:0] first shows the size of the transfer and then shows
the port size.
Freescale Semiconductor, Inc.
Table 17-4. Bus Cycle Size Encoding
For More Information On This Product,
Chapter 17. Signal Descriptions
SIZ[1:0]
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00
01
10
11
Longword
Byte
Word
Line
Port Size
MCF5307 Bus Signals
17-9