MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 187
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MCF5307CFT66B
Manufacturer Part Number
MCF5307CFT66B
Description
IC MPU 32BIT 66MHZ COLDF 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307CFT66B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number:
MCF5307CFT66B
Manufacturer:
FREESCAL
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Part Number:
MCF5307CFT66B
Manufacturer:
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When the watchdog timer times out and SYPCR[SWRI] is programmed for a software
reset, an internal reset is asserted and RSR[SWTR] is set.
To prevent the watchdog timer from interrupting or resetting, the SWSR must be serviced
by performing the following sequence:
Both writes must occur in order before the timeout, but any number of instructions or
SWSR accesses can be executed between the two writes. This order allows interrupts and
exceptions to occur, if necessary, between the two writes.
Caution should be exercised when changing SYPCR values after the software watchdog
timer has been enabled with the setting of SYPCR[SWE], because it is difficult to
determine the state of the watchdog timer while it is running. The countdown value is
constantly compared with the timeout period specified by SYPCR[SWP,SWT]. Therefore,
altering SWP and SWT improperly causes unpredictable processor behavior. The following
steps must be taken to change SWP or SWT:
SYPCR[SWTAVAL]
Figure 6-4. MCF5307 Embedded System Recovery from Unterminated Access
1. Write 0x55 to SWSR.
2. Write 0xAA to the SWSR.
timer IRQ
watchdog
watchdog
Software
Software
timer TA
Code enables software watchdog timer interrupt and
SWTA functionality by writing SYPCR.
1
1
SWTAVAL is set if watchdog timer TA is asserted.
Freescale Semiconductor, Inc.
For More Information On This Product,
1. Watchdog timer times out due to unterminated bus
2. Watchdog timer interrupt cannot be serviced due to hung bus
Problem:
cycle. Wait for another timeout before setting SYPCR[SWTA].
Timeout
Chapter 6. SIM Overview
Go to: www.freescale.com
NOTE: The watchdog timer IRQ should
be set to the highest level in the system.
Timeout
3. TA held until another
bus cycle starts
Code in the watchdog timer interrupt
handler polls SYPCR[SWTAVAL] to
determine if SWT TA was needed. If so,
execute code to identify bad address.
Watchdog timer
IACK cycle
Programming Model
6-7
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