MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 427

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.3 TAP Controller
The state of TMS at the rising edge of TCK determines the current state of the TAP
controller. The TAP controller can follow two basic two paths, one for executing JTAG
instructions and the other for manipulating JTAG data based on JTAG instructions. The
various states of the TAP controller are shown in Figure 19-2. For more detail on each state,
see the IEEE Standard 1149.1 JTAG document. Note that regardless of the TAP controller
state, test-logic-reset can be entered if TMS is held high for at least five rising edges of
TCK. Figure 19-2 shows the JTAG TAP controller state machine.
TDI/DSI
DSCLK
TRST/
TDO/
DSO
Pin
for loading the JTAG boundary-scan, bypass, and instruction registers. Shifting in of data depends on the
state of the JTAG controller state machine and the instruction in the instruction register. This shift occurs on
the rising edge of TCK. TDI has an internal pull-up so if it is not driven low its value defaults to a logical 1. If
TDI is not used, it should be tied to VDD.
DSI provides single-bit communication for debug module commands. See Chapter 5, “Debug Support.”
Test data output (MTMOD0 high)/development serial output (MTMOD0 low). TDO is the serial data port for
outputting data from JTAG logic. Shifting data out depends on the state of the JTAG controller state
machine and the instruction currently in the instruction register. This shift occurs on the falling edge of TCK.
When not outputting test data, TDO is three-stated. It can also be placed in three-state mode to allow
bussed or parallel connections to other devices having JTAG. DSO provides single-bit communication for
debug module commands. See Chapter 5, “Debug Support.”
Test reset (MTMOD0 high)/development serial clock (MTMOD0 low). As TRST, this pin asynchronously
resets the internal JTAG controller to the test logic reset state, causing the JTAG instruction register to
choose the IDCODE instruction. When this occurs, all JTAG logic is benign and does not interfere with
normal MCF5307 functionality. Although this signal is asynchronous, Motorola recommends that TRST
make only an asserted-to-negated transition while TMS is held at a logic 1 value. TRST has an internal
pull-up; if it is not driven low its value defaults to a logic level of 1. However, if TRST is not used, it can
either be tied to ground or, if TCK is clocked, to VDD. The former connection places the JTAG controller in
the test logic reset state immediately; the latter connection eventually puts the JTAG controller (if TMS is a
logic 1) into the test logic reset state after 5 TCK cycles.
DSCLK is the development serial clock for the serial interface to the debug module.The maximum DSCLK
frequency is 1/2 the BCLKO frequency. See Chapter 5, “Debug Support.”
Test data input (MTMOD0 high)/development serial input (MTMOD0 low). TDI provides the serial data port
Chapter 19. IEEE 1149.1 Test Access Port (JTAG)
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 19-1. JTAG Pin Descriptions
Go to: www.freescale.com
Description
TAP Controller
19-3