MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 57

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Intended Audience
Part I is intended for system designers who need a general understanding of the
functionality supported by the MCF5307. It also describes the operation of the MCF5307
Contents
• Chapter 2, “ColdFire Core,” provides an overview of the microprocessor core of the
• Chapter 3, “Hardware Multiply/Accumulate (MAC) Unit,” describes the MCF5307
• Chapter 4, “Local Memory.” This chapter describes the MCF5307 implementation
• Chapter 5, “Debug Support,” describes the Revision C enhanced hardware debug
MCF5307. The chapter begins with a description of enhancements from the V2
ColdFire core, and then fully describes the V3 programming model as it is
implemented on the MCF5307. It also includes a full description of exception
handling, data formats, an instruction set summary, and a table of instruction
timings.
multiply/accumulate unit, which executes integer multiply, multiply-accumulate,
and miscellaneous register instructions. The MAC is integrated into the operand
execution pipeline (OEP).
of the ColdFire V3 local memory specification. It consists of the two following
major sections.
— Section 4.2, “SRAM Overview,” describes the MCF5307 on-chip static RAM
— Section 4.7, “Cache Overview,” describes the MCF5307 cache implementation,
support in the MCF5307. This revision of the ColdFire debug architecture
encompasses earlier revisions.
(SRAM) implementation. It covers general operations, configuration, and
initialization. It also provides information and examples showing how to
minimize power consumption when using the SRAM.
including organization, configuration, and coherency. It describes cache
operations and how the cache interacts with other memory structures.
Freescale Semiconductor, Inc.
For More Information On This Product,
Part I. MCF5307 Processor Core
MCF5307 Processor Core
Go to: www.freescale.com
Part I
I-xvii