MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet - Page 75

• Manufacturer Part Number: MCF5307CFT66B
• Description: IC MPU 32BIT 66MHZ COLDF 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307CFT66B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

<ea>y,<ea>x
Instruction
# <vector>
MACSR
#<data>
<label>
DDATA
<shift>
<size>
MASK
Dy,Dx
Ry,Rx
<xxx>
Ay,Ax
<list>
CCR
Í
ACC
PST
Rm
Rw
PC
SR
An
Dn
Rc
Rn
SF
uc
dn
Xi
Effective address
identifies an indirect data address referencing memory
Any address register n (example: A3 is address register 3)
Source and destination address registers, respectively
Any data register n (example: D5 is data register 5)
Source and destination data registers, respectively
Any control register (example VBR is the vector base register)
MAC registers (ACC, MAC, MASK)
Any address or data register
Destination register w (used for MAC instructions only)
Any source and destination registers, respectively
index register i (can be an address or data register: Ai, Di)
MAC accumulator register
Condition code register (lower byte of SR)
MAC status register
MAC mask register
Program counter
Status register
Debug data port
Processor status port
Immediate data following the 16-bit operation word of the instruction
Source and destination effective addresses, respectively
Assembly language program label
List of registers for MOVEM instruction (example: D3–D0)
Shift operation: shift left (<<), shift right (>>)
Operand data size: byte (B), word (W), longword (L)
Unified cache
Identifies the 4-bit vector number for trap instructions
identifies an absolute address referencing memory
Signal displacement value, n bits wide (example: d16 is a 16-bit displacement)
Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations)
Table 2-6. Notational Conventions (Continued)
Freescale Semiconductor, Inc.
For More Information On This Product,
Chapter 2. ColdFire Core
Go to: www.freescale.com
Miscellaneous Operands
Register Specifications
Register Names
Port Name
Operand Syntax
Instruction Set Summary
2-35